The present invention relates generally to integrated circuits and relates more specifically to metal patterning processes for use in manufacturing integrated circuits.
Integrated circuits (ICs) commonly use copper interconnects (or “lines”) to connect transistors and other semiconductor devices on the ICs. As the size of these interconnects scales down, however, challenges in the manufacturing process increase. For instance, at the thirty-two nanometer node, one may have to contend with incomplete fills during electroplating, damage to the dielectric during trench reactive ion etching (RIE), and shorting due to difficulties associated with line capping. Further scaling of the interconnects not only exacerbates these problems, but also introduces new problems.
Moreover, even assuming that the technical hurdles associated with manufacturing can be overcome, it is expected that at some dimension, the copper will simply fail to conduct electricity effectively.